1. Field of the Invention
The present invention generally relates to testing of integrated circuits (ICs) as part of the manufacturing process and, more particularly, to on-chip circuitry which facilitates fuse testing in customized integrated circuits. The invention has specific application in testing fuse redundancy high end memories.
2. Description of the Prior Art
Redundancy in integrated circuit memories is part of current wafer and chip manufacturing strategy to improve yield. The practice is to blow fuses which allow extra memory cells to be used in place of cells that are non-functional. Fuses have been used in lower performance products where the method of blowing the fuses is with a laser. This is not practical in high performance products and, therefore, the preferred method of blowing the fuses is by means of high currents.
The simplification of the fuse blow procedure afforded by using high currents is but one part of the cost of the manufacturing equation. The need for improving test methodologies is also extremely important in the manufacturing environment. Test costs have been driven higher and higher as devices become more complex. The goal is to maintain or increase the quality of the test while minimizing the cost of the test and decreasing product losses resulting from poor quality as determined by the test. It is not an easy task to achieve these conflicting requirements in the high end product environment when performance and cost are the key ingredients to remain competitive.
The fuse blow procedure, combined with current test apparatus, does have a serious drawback. Specifically, once the fuses have been blown, the chip has been permanently altered. The problem is that with current test apparatus, a "false fail" pattern may develop leading to the blowing of fuses for chips which actually do not have defective blocks. If the number of blocks indicated as "failed" by the test apparatus exceeds the number of fuses available to correct for the "false fails", fuses will be blown until the number of blocks needing correction exceeds the number of fuses resulting in a rejection of the chip. Thus, chips which may in fact be good or correctable will be rejected until the "false fail" pattern or syndrome is detected and corrected.